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12 WDOG - Watchdog Timer
Quick Facts
What?
The WDOG (Watchdog Timer) resets the
system in case of a fault condition, and can
0 1 2 3
4
be enabled in all energy modes as long as
the low frequency clock source is available.
Why?
Counter value
Watchdog clear
System reset
If a software failure or external event renders
the MCU unresponsive, a Watchdog timeout
will reset the system to a known, safe state.
Tim eout period
Tim e
How?
An enabled Watchdog Timer implements a
configurable timeout period. If the CPU fails
to re-start the Watchdog Timer before it times
out, a full system reset will be triggered. The
Watchdog consumes insignificant power,
and allows the device to remain safely in low
energy modes for up to 256 seconds at a
time.
12.1 Introduction
The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase
application reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or
by a software failure.
12.2 Features
? Clock input from selectable oscillators
? Internal 32.768 kHz RC oscillator
? Internal 1kHz RC oscillator
? External 32.768 kHz XTAL oscillator
? Configurable timeout period from 9 to 256k watchdog clock cycles
? Individual selection to keep running or freeze when entering EM2 or EM3
? Selection to keep running or freeze when entering debug mode
? Selection to block the CPU from entering Energy Mode 4
? Selection to block the CMU from disabling the selected watchdog clock
12.3 Functional Description
The watchdog is enabled by setting the EN bit in WDOG_CTRL. When enabled, the watchdog counts
up to the period value configured through the PERSEL field in WDOG_CTRL. If the watchdog timer is
not cleared to 0(by writing a 1 to the CLEAR bit in WDOG_CMD) before the period is reached, the chip
is reset. If a timely clear command is issued, the timer starts counting up from 0 again. The watchdog
can optionally be locked by writing the LOCK bit in WDOG_CTRL. Once locked, it cannot be disabled
or reconfigured by software.
The watchdog counter is reset when EN is reset.
2011-04-12 - d0001_Rev1.10
121
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